The cache location being flipped mitigates some of the clock speed gap (and I personally don’t like how inefficient recent-gen CPUs are in lightly threaded workloads, so skimming 5% off the 1T clockspeed without affecting the nT clockspeed isn’t much of a con for me personally). I don’t mind being virtually-imperceptibly (<5%) slower in workloads that are not sensitive to cache if the tradeoff is having the workloads that are sensitive to cache always, without fail gaining that respective benefit.

Or maybe I’m completely wrong, and they’ll release a dual 3d cache cpu a couple months after they start selling the 9950x3d to maximize profit

Haha, I think they would have both a branding problem for the SKU (what do they call it?), and significant backlash from both press and the public if they did that, but it’s not unheard of for a hardware manufacturer to trip over themselves doing something like that :P