At less than a tenth the size, this is actually a better explanation than the article. Already correcting the fact that we do at the very beginning.
If you absolutely had to put a bit width on the Zen 4, the 2x128 bit data bus is probably the best single measure totaling 256 bit IMO.
Even then, at what point do you measure it? DDR interface is likely very much narrower than the interfaces between cache levels. Where does the core end and the memory begin?
Yes you are 100% right, and I did consider level 3 cache as a better measure, because that allows communication between cores without the need to go through RAM, and cache generally has a high hit rate. But this number was surprisingly difficult to find, so I settled on the data bus.
Anyways it would be absolutely fair to call it 256bit by more than one measure. But for sure it isn’t just 64 bit, because it has 512 bit instructions, so the instruction set isn’t limited to 64 bit. Even if someone was stubborn enough to claim the general instruction set is 64 bit, it has the ability to decode and execute 2 simultaneous 64 bit instructions per core, making at least 128 bit by any measure.
