Maybe, but the point is that it’s open. There’s a much higher chance that one of the companies that builds parts will make good decisions.
RISC-V is the only shot we have at usable open source hardware. I really, really hope it takes off.
Whilst some open source implementations exist, RISC-V is not open source. It’s an open standard. i.e. there’s no license fee to implement it.
I didn’t know that I thought all RISC-V was open source :( I’m not as familiar with it as I’d like to be. I might just have to dive into it more and change that soon
smells like linus thinks there is going to be an ever increasing tech debt, and honestly, i think i agree with him on that one.
RISCV is likely going to eventually overstep it’s role in someplaces, and bits and pieces of it will become archaic over time.
The gap between hardware and software level abstraction is huge, and that’s really hard to fill properly. You just need a strict design criteria to get around that one.
I’m personally excited to see where RISCV goes, but maybe what we truly need is a universal software level architecture that can be used on various different CPU architectures providing maximum flexibility.
software level architecture that can be used on various different CPU architectures providing maximum flexibility.
I’ve only done a little bare metal programming, but I really don’t see how this is possible. Everything I’ve used is so vastly different, I think it would be impossible to create something like that, and have it work well.
theoretically you could do it by defining an architecture operations standard, and then adhering to that somewhat when designing a CPU. While providing hardware flexibility as you could simply, not implement certain features, or implement certain other features. Might be an interesting idea.
That or something that would require minimal “instruction translation” between different architectures.
It’s like x86. except if most of the features were optional.
It sounds like you’re just reinventing either the JVM (runtime instruction translation), compilers (LLVM IR), or something in between (JIT interpreters).
The problem is that it’s a hard problem to solve generally without expensive tradeoffs:
- interpreter like JVM - will always have performance overhead and can’t easily target arch-specific optimizations like SIMD
- compiler - need a separate binary per arch, or have large binaries that can do multiple
- JIT - runtime cost to compiling optimizations
Each is fine and has a use case, but I really don’t think we need a hardware agnostic layer, we just need languages that help alleviate issues with different architectures. For example, Rust’s ownership model may help prevent bugs that out of order execution may expose. It could also allow programmers to specify more strict limits on types (e.g. non-zero numbers, for example), which could aid arch-specific optimizations).
but maybe what we truly need is a universal software level architecture that can be used on various different CPU architectures providing maximum flexibility.
I think that’s called Java.
Then again, if you don’t have the JVM/JRE, Java won’t work, so first you need to write it in another language and in such a way that it works across a bunch of different ARM and x86 processors.
I don’t know, if your platform doesn’t have a jre… Is it really a platform?
It’s open source nature protects against that. People mistake Linus as being in the same boat as Stallman but Linus was only open source by circumstance, he kind infamously doesn’t seem to appreciate the role open source played in his own success.
It already directly addresses the mistakes of x86 and ARM. I don’t know what he is so worried about.
Protects against what?
What I read here is just a vague critic from him of the relation between hard- and software developer. Which will not change just because the ISA is open source. It will take some iterations until this is figured out, this is inevevable.
Soft- and hardware developers are experts in their individual fields, there are not many with enough know-how of both fields to be effective.
Linus also points out, that because of ARM before, RISC-V might have a easier time, on the software side, but mistakes will still happen.
IMO, this article doesn’t go into enough depths of the RISC-V specific issues, that it warrants RISC-V in the title, it would apply to any up and coming new ISA.
Only the core part of the ISA is open source. Vendors are free to add whatever proprietary extensions they want and sell the resulting CPU.
You might get such a CPU to boot, but getting all functionality might be the same fight it is with arm CPUs currently.
I’ll say to you what I said to the other commentor: RISC-V is an ISA, nothing less, nothing more, and it is 100% open-source. It is not trying to be anything else. Yes, hardware implementations from processor vendors can have different licensing and be proprietary, but that is not the fault of RISC-V, nor does that have anything else to do with it. RISC-V, as an ISA, and only an ISA, is completely open-source and not liable for the bs of OEMs.
