Why is everything RISC-V some low power device, I want a workstation with PCIe 5.0 powered by RISC-V.
I’d guess they’d need to figure out whatever apple did with it’s arm chips.
efficient use of many-cores and probably some fancy caching arrangement.
It’ll may also be a matter of financing to be able to afford (compete with intel, apple, amd, nvidia) to book the most advanced manufacturing for decent sized batches of more complex chips.
Once they have proven reliable core/chip designs , supporting more products and a growing market share, I imagine more financing doors will open.
I’d guess risc-v is mostly financed by industry consortia maybe involving some governments so it might not be about investor finance, but these funders will want to see progress towards their goals. If most of them want replacements for embedded low power arm chips, that’s what they’re going to prioritise over consumer / powerful standalone workstations.
At a minimum they’ve got to design a wider issue. Current high-performance superscalar chips like the XuanTie 910 (what this laptop’s SoC are built around) are only triple-issue (3-wide superscalar), which gives a theoretical maximum of 3 ipc per core. (And even by RISC standards, RISC-V has pretty “small” instructions, so 3 ipc isn’t much compared to 3 ipc even on ARM. E.g., RISC-V does not have any comparison instructions, so comparisons need to be composed of at least a few more elementary instructions). As you widen the issue, that complicates the pipelining (and detecting pipeline hazards).
There’s also some speculation that people are going to have to move to macro-op fusion, instead of implementing the ISA directly. I don’t think anyone’s actually done that in production yet (the macro-op fusion paper everyone links to was just one research project at a university and I haven’t seen it done for real yet). If that happens, that’s going to complicate the core design quite a lot.
None of these things are insurmountable. They just take people and time.
I suspect manufacturing is probably a big obstacle, too, but I know quite a bit less about that side of things. I mean a lot of companies are already fabbing RISC-V using modern transistor technologies.
I think that’s the whole point of all risc - it saves power over cisc but may take longer to compute some tasks.
That’d be why things like phones with limited batteries often prefer risc.
That’s true for small and simple microcontrollers, but larger and more complicated ones can theoretically implement macro operation fusion in hardware to get similar benefits as CISC architectures
It definitely could scale up. The question is who is willing to scale it up? It takes a lot less manpower, a lot less investment, and a lot less time to design a low-power core, which is why those have come to market first. Eventually someone’s going to make a beast of a RISC-V core, though.
milk-v is going to release a pretty powerful system, iirc i read it will be released in about 10 months, ventana also reportedly will release a server cpu in 2024.
It takes time, as it all is under heavy development. Just since very recently there are risc v sbc available that can run linux - before it was pretty much microcontrollers only. Be patient :)
Even once the kinks are worked out, the primary market for RISC-V will be low-end. It’s a FOSS (FOSH?) upgrade path from 8-bit and 16-bit ISAs.
There will be no reason for embedded systems to use ARM.
Initial market, absolutely. It’s already there at this point. Low power 32-bit ARM SoC MCUs have largely replaced the 8-bit and 16-bit AVR MCUs, as well as MIPS in new designs. They’ve just been priced so well for performance and relative cost savings on the software/firmware dev side (ex. Rust can run with its std library on Espressif chips, making development much quicker and easier).
With ARM licensing looking less and less tenable, more companies are also moving to RISC-V from it, especially if they have in-house chip architects. So, I also suspect that it will supplant ARM in such use cases - we’re already seeing such in hobbyist-oriented boards, including some that use a RISC-V processor as an ultra-low-power co-processor for beefier ARM multi-core SoCs.
That said, unless there’s government intervention to kill RISC-V, under the guise of chip-war (but really likely because of ARM “campaign contributions”), I suspect that we’ll have desktop-class machines sooner than later (before the end of the decade).
I would’ve had my doubts, until Apple somehow made ARM competitive with x86. A trick they couldn’t pull off with PowerPC.
I guess linear speed barely ought to matter, these days, since parallelism is an order-of-magnitude improvement, and scales.
Does the trackpoint work like an old IBM thinkpad? If so this would be a really neat computer.
Are netbooks making a comeback?
Does RISC-V have security benefits since it is open source? Is it easier to detect hardware backdoors if it is used instead of x86 or ARM?
RISC-V instruction set (ISA) is open source. But the actual implementation (microarchitecture) has no such obligations. And among the implementations that can run Linux, none (that I know) are open source designs.
With regards to hardware backdoors - no, closed source RISC-V implementations are not easier than x86 or ARM to audit for security.
Does it run GNU/Linux?