And modern X86 chips are in fact NOT 64 bit anymore, but hybrids that handle tasks with 256 bits routinely, and some even with 512 bits, with instruction extensions that have become standard on both Intel and AMD
On a note of technical correctness: That’s not what the bitwidth of a CPU is about.
By your account a 386DX would be an 80-bit CPU because it could handle 80-bit floats natively, and the MOS6502 (of C64 fame) a 16-bit processor because it could add two 16-bit integers. Or maybe 32 bits because it could multiply two 16-bit numbers into a 32-bit result?
In reality the MOS6502 is considered an 8-bit CPU, and the 386 a 32-bit one. The “why” gets more complicated, though: The 6502 had a 16 bit address bus and 8 bit data bus, the 368DX a 32 bit address and data bus, the 368SX a 32 bit address bus and 16 bit external data bus.
Or, differently put: Somewhere around the time of the fall of the 8 bit home computer the common understanding of “x-bit CPU” switched from data bus width to address bus width.
…as, not to make this too easy, understood by the instruction set, not the CPU itself: Modern 64 bit processors use pointers which are 64 bit wide, but their address buses usually are narrower. x86_64 only requires 48 bits to be actually usable, the left-over bits are required to be either all ones or all zeroes (enforced by hardware to keep people from bit-hacking and causing forwards compatibility issues, 1/0 IIRC distinguishes between user vs. kernel memory mappings it’s been a while since I read the architecture manual). Addressable physical memory might even be lower, again IIRC. 248B are 256TiB no desktop system can fit that much, and I doubt the processors in there could address it.
By your account a 386DX would be an 80-bit
And how do you figure that? The Intel 80386DX did NOT have any 80 bit instructions at all, the built in math co-processor came with i486. The only instructions on a 80386DX system that would be 80 bit would be to add a 80387 math co-processor.
But you obviously don’t count by a few extended instructions, but by the architecture of the CPU as a whole. And in that regard, the Databus is a very significant part, that directly influence the speed and number of clocks of almost everything the CPU does.
The Intel 80386DX did NOT have any 80 bit instructions at all, the built in math co-processor came with i486.
You’re right, I misremembered.
And in that regard, the Databus is a very significant part, that directly influence the speed and number of clocks of almost everything the CPU does.
For those old processors, yes, that’s why the 6502 was 8-bit, for modern processors, though? You don’t even see it listed on spec sheets. Instead, for the external stuff, you see number of memory controllers and PCIe lanes, while everything internal gets mushed up in IPC. “It’s wide enough to not stall the pipeline what more do you want” kind of attitude.
Go look at anything post-2000: 64 bit means that pointers take up 64 bits. 32 bits means that pointers take up 32 bits. 8-bit and 16-bit are completely relegated to microcontrollers, I think keeping the data bus terminology, and soonish they’re going to be gone because everything at that scale will be RISC-V, where “RV32I” means… pointers. So does “RV64I” and “RV128I”. RV16E was proposed as an April Fool’s joke and it’s not completely out of the question that it’ll happen. In any case there won’t be RV8 because CPUs with an 8-bit address bus are pointlessly small, and “the number refers to pointer width” is the terminology of <currentyear>. An RV16 CPU might have a 16 bit data bus, it might have an 8 bit data bus, heck it might have a 256bit data bus because it’s actually a DSP and has vector instructions. Sounds like a rare beast but not entirely nonsensical.
You don’t even see it listed on spec sheets.
Doesn’t mean it’s any less important, it’s just not a good marketing measure,because average people wouldn’t understand it anyway, and it wouldn’t be correct to measure by the Databus alone.
As I stated it’s MORE complex today, not less, as the downvoters of my posts seem to refuse to acknowledge. The first Pentium had a 64 bit Databus for a 32 bit CPU. Exactly because data transfer is extremely important. The first Arm CPU was designed around as fast RAM access/management as possible, and it beat the 386 by several factors, with a tenth the transistors.
Go look at anything post-2000: 64 bit means that pointers take up 64 bits. 32 bits means that pointers take up 32 bits.
Although true, this is a very simplistic way to view it, and not relevant to the actual overall bitwith of the CPU, as I’ve tried to demonstrate, but people apparently refuse to acknowledge.
But bit width of the Databus is very important, and it was debated heavily weather it was even legal to market the M68008 Sinclair QL as a 32 bit computer, because it only had an 8 bit databus.
But as I stated other factors are equally important, and the decoder is way more important than the core instruction set, and modern higher end decoders operate at 256 bit or more, allowing them to decode multiple ( 4 ) instructions per cycle, again allowing each core to execute multiple instructions per clock, in 2 threads. Without that capability, each core would only be about a third as fast.
To claim that the instruction set determines bit wdth is simplistic, and also you yourself argued against it, because that would mean an i486 would be an 80 bit CPU. And obviously todays CPU’s would be 512 bit, because they have 512 bit instructions.
Calling it 64 bit is exclusively meant to distinguish newer CPU’s from older 32 bit CPUS, and we’ve done that since the 90’s, claiming that new CPU architectures haven’t increased in bit width for 30 years is simply naive and false, because they have in many more significant ways than the base instruction set.
Still I acknowledge that an AARCH64 or AMD64 or i64 CPU are generally called 64 bit, it was never the point to refute that. Only that it’s a gross simplification of what modern CPU’s have become, and that it’s not technically correct.
Let me finish with a question:
With a multi-core CPU where each core is let’s just say 64 bit, how many bits is the whole CPU package? Which is what we call the “CPU” today, when saying CPU we are not generally talking about the individual cores, because then it would have to be plural.
By your account a 386DX would be an 80-bit CPU because it could handle 80-bit floats natively,
No that’s not true, it’s way way more complex than that, some consider the data bus the best measure, another could be decoder. I could also have called a normal CPU bitwidth as depending on how many cores it has, each core handling up to 4 instructions per cycle, could be 256 bit, with an average 8 core CPU that would be 2048 bit.
There are several ways to evaluate like Databus, ALU, Decoder etc, but most ways to measure it reasonably hover around the 256 bit, and none below 128 bit.
There is simply no reasonable way to argue a modern Ryzen CPU or Intel equivalent is below 128 bit.
There is simply no reasonable way to argue a modern Ryzen CPU or Intel equivalent is below 218 bit.
There absolutely is, and the person you responded to made it incredibly clear: address width. Yeah, we only use 48-bit addresses, but addresses are 64-bit, and that’s the key difference that the majority of the market understands between 32-bit and 64-bit processors. The discussion around “32-bit compatibility” is all about address size.
And there’s also instruction size. Yes, the data it operates on may be bigger than 64-bit, but the instructions are capped at 64-bit. With either definition, current CPUs are clearly 64-bit.
But perhaps the most important piece here is consumer marketing. Modern CPUs are marketed as 64-bit (based on both of the above), and that’s what the vast majority of people understand the term to mean. There’s no point in coming up with another number, because that’s not what the industry means when they say a CPU is 64-bit or 32-bit.
Edited for clarity
ddresses, but addresses are 64-bit
You are stating the register width, which is irrelevant to the width of the address bus. But that doesn’t make a shred of sense. it’s like claiming a road is 40000 km long around the globe, it’s just not finished, so you can only drive on a few km of it. The registers are 64 bit, but “only” 40 can be used. Enough to address 1 Terabyte of RAM.
If you want to measure by Address width we don’t have a single 64 bit CPU, because there doesn’t exist a 64 bit CPU that has a 64 bit Address bus.
